This invention relates generally to semiconductor metallization processing methods for imparting multi-level electrical interconnection.
Multi-level metallization is a critical area of concern in advanced semiconductor fabrication where designers continue to strive for circuit density maximization. Metallization interconnect techniques typically require electrical connection between metal layers or runners occurring at different elevations within a semiconductor substrate. Such is typically conducted, in part, by etching a contact opening through insulating material to the lower elevation metal layer. Increased circuit density has resulted in narrower and deeper electrical contact openings between layers within the substrate. Adequate contact coverage within these deep and narrow contacts continues to challenge the designer.
Aluminum and aluminum alloys remain the principle metallization materials of choice due to their high conductivities. However, deep and narrow contact openings are very difficult to fill by conventional aluminum deposition techniques. Such techniques are principally limited to sputter deposition.
One way of overcoming this problem is to chemical vapor deposit (CVD) another more conformal metal, such as tungsten, which enables complete contact filling. CVD tungsten would typically completely fill a contact opening, where sputter deposition of aluminum would not. Techniques for CVD of aluminum have yet to be developed. Use of tungsten is not without drawbacks. For example, tungsten has three times the resistivity of aluminum, which can result in parts with lower speed or increased die size to provide for wider tungsten lines for obtaining desired current flow. In addition to resistivity problems, tungsten does not bond readily to other commonly used semiconductor metals, such as gold or aluminum.
One technique for making multi-level metal electrical interconnection in ULSI processing involves groove and fill techniques, such as is described in Kaanta, et al., xe2x80x9cDual damascene: A ULSI Wiring Technologyxe2x80x9d, a paper submitted at the Jun. 11-12, 1991 VMIC Conference sponsored by the IEEE. Such reference describes a technique whereby a combination of contact openings is provided through an insulating layer to active areas, and a groove pathway is as well etched at the top of the insulating layer. Thereafter, a single layer of tungsten metal is deposited to completely fill the contact openings and pathway. A subsequent planarization is conducted to the upper level of the insulating layer to define isolated finished conductive lines or runners.
Improvements still need to be made to such techniques for further maximization of circuit density and to accommodate or allow use of sputtered aluminum for second or upper level metallization. One prior art drawback is described with reference to FIGS. 1-3. FIG. 1 illustrates a semiconductor wafer fragment 10 comprised of a bulk substrate 12 having a planarized insulating layer 14, such as SiO2. Another planarized insulating layer 16 is provided atop layer 14, and provided with a pair of etched groove pathways 18, 20 (see also FIG. 3). A metal layer 22, preferably predominantly aluminum such as sputtered deposited aluminum, is provided atop layer 16 and completely fills within groove pathways 18, 20.
Referring to FIGS. 2 and 3, layer 22 is planarized by chemical-mechanical polishing techniques back to at least the upper surface of insulator layer 16 to define electrically isolated conductive first level metal runners 24 and 26. Another layer of insulating material 28 is provided atop the wafer. A masking and etch of layer 28 are then provided to produce contact openings 30, 32 for ultimately connecting a higher metal layer to runners 24 and 26. It is important to conduct such etching for a time sufficient to insure complete passage through material 28 to reach the upper surface of the runners 24 and 26. Accordingly, if the photomask alignment were not precise such that openings 30 and 32 were to overlap with portions of runners 24 and 26 and with layer 16, undesired over etch into layer 16 would occur.
To prevent or allow for such misalignment, enlarged surround areas 34, 36 are provided when etching layer 16 to form groove pathways 18, 20. It will be appreciated that such enlarged areas necessitate positioning conductive lines 18 and 20 farther apart than were such surround areas 34 and 36 not provided. Accordingly, providing such surround areas works against maximizing circuit density.
FIG. 4 illustrates the problem associated with overetch where a metal 2 to metal 1 contact opening is misaligned. There illustrated is a wafer fragment 10a having a misaligned metal 2 to metal 1 contact opening 30a, with there being no surround area to accommodate such eventual mask misalignment. The etch of layer 28 causes a recess or pocket 38 to form externally adjacent runner 26. Again, the desired material for second or higher level metallization is predominantly aluminum which is typically deposited by sputter deposition. FIG. 4 illustrates a sputter deposited aluminum layer 40 which, because of recess or pocket 38, does not adequately fill contact opening 30a. Such creates the illustrated discontinuity in layer 40.
FIG. 5 illustrates a technique for overcoming problems associated with the potential above-described metal 2 to metal 1 discontinuity. Here, a wafer fragment 10b having misaligned metal 2 to metal 1 contact opening 30a acquires a highly conformal chemical vapor deposited layer of tungsten 42. Such layer is planarized back to define a conductive plug or via 42 of tungsten. Thereafter, a layer 44 of aluminum can be provided and patterned as illustrated. While overcoming the discontinuity problem referred to above, the FIG. 5 technique adds the additional processing steps of adding a CVD tungsten deposition, requiring an associated xe2x80x9cgluexe2x80x9d layer, and subsequent etchback. These additional processing steps increase wafer processing cost and lowers yield by adding defects.
It would be preferable if all or the metal 2 layer were predominately comprised of aluminum. Further, it would be desirable to develop improved interlevel metallization interconnection schemes involving groove and fill, or damascene, processes of a first or lower level metal followed by the utilization of a sputtered aluminum for the upper level metal, and which do not fundamentally require formation of space-consuming surround of a via by the lower level metal.